# User Contributed Dictionary

### Noun

- The state or property of being capable of being verified; confirmability.

#### Quotations

- 1887, J. M. Rigg, "The Place of Hypothesis in Experimental
Science," Mind, vol. 12, no. 48, p. 559,
- Mill distinguished between hypotheses which rest on mere analogy and such as are capable of "being ultimately brought to the test of actual induction," claiming for the latter a verifiability which he denied to the former.

- 1973 , James C. McKeown, "Comparative Application of Market and
Cost Based Accounting Models," Journal of Accounting Research, vol.
11, no. 1, p. 99,
- The verifiabilities of the other measurement systems were very similar.

- 2004, Mark Sanders, "Truths and Contestation: Literature in
Law," Law and Literature, vol. 16, no. 3, p. 481,
- The issues of veracity and verifiability raised by testimony in trials emerge with a vengeance in the context of the Truth and Reconciliation Commission.

# Extensive Definition

In the context of hardware and software systems,
formal verification is the act of proving
or disproving the correctness of intended
algorithms underlying
a system with respect to a certain formal specification or
property, using formal
methods of mathematics.

portal Software
Testing

## Usage

Formal verification can be used for example for
systems such as cryptographic
protocols, combinational
circuits, digital
circuits with internal memory, and software expressed as source
code.

The verification of these systems is done by
providing a formal proof on an abstract mathematical model of the
system, the correspondence between the mathematical model and the
nature of the system being otherwise known by construction.
Examples of mathematical objects often used to model systems are:
finite
state machines, labelled
transition systems, Petri nets,
timed
automata, hybrid
automata, process
algebra, formal semantics of programming languages such as
operational
semantics, denotational
semantics, axiomatic
semantics and Hoare
logic.

## Approaches to formal verification

There are roughly two approaches to formal
verification.

The first approach is model
checking, which consists of a systematically exhaustive
exploration of the mathematical model (this is possible for finite
models, but also for some infinite models where infinite sets of
states can be effectively represented). Usually this consists of
exploring all states and transitions in the model, by using smart
and domain-specific abstraction techniques to consider whole groups
of states in a single operation and reduce computing time.
Implementation techniques include state
space enumeration, symbolic state space enumeration, abstract
interpretation, symbolic
simulation, abstraction
refinement.

The second approach is logical inference. It
consists of using a formal version of mathematical reasoning about
the system, usually using theorem proving software such as a
HOL
theorem prover, the ACL2
theorem prover or the Isabelle
theorem prover. This is usually only partially automated and is
driven by the user's understanding of the system to validate.

The properties to be verified are often described
in temporal
logics, such as linear
temporal logic (LTL) or computational
tree logic (CTL).

## Validation and Verification

Verification is one aspect of testing a product's
fitness for purpose. Validation is
the complementary aspect. Often one refers to the overall checking
process as V & V.

- Validation: "Are we trying to make the right thing?", i.e., does the product do what the user really requires?
- Verification: "Have we made what we were trying to make?", i.e., does the product conform to the specifications?

The verification process consists of static and
dynamic parts. E.g., for a software product one can inspect the
source code (static) and run against specific test cases (dynamic).
Validation usually can only be done dynamically, i.e., the product
is tested by putting it through typical usages and atypical usages
("Can we break it?"). See also
Verification and Validation

## See also

## External links

- Prover iLock, Signaling Design Automation Tool Suite
- EmbeddedValidator, Matlab/Simulink/Stateflow/Targetlink Formal Verification Environment
- Statemate ModelChecker, Statemate Models Robustness Checking
- Statemate ModelCertifier, Statemate Models Requirements Certification
- Prover Plug-In, a widely used commercial formal verification engine
- GC6 - The Verification Grand Challenge for Computing
- Polyspace Technologies and the Polyspace Verifier
- The ESC/Java program verifier and Simplify theorem-prover
- The SMVS formal verification project at Man-Made Minions
- The SPARK Ada language and SPARK Examiner verification toolset
- The Spec# language, compiler and program verifier
- LDRA and the LDRA tool suite
- The KeY verification system
- The VectorCAST tool suite for C/C++ and Ada unit and integration testing

verifiability in Czech: Formální
verifikace

verifiability in German: Verifizierung

verifiability in Spanish: Verificación
formal

verifiability in French: Vérification
formelle

verifiability in Hebrew: אימות תוכנה

verifiability in Japanese: 形式的検証

verifiability in Norwegian: Verifikasjon

verifiability in Polish: Weryfikacja
formalna

verifiability in Russian: Формальная
верификация

verifiability in Slovak: Verifikácia

verifiability in Serbian: Верификација

verifiability in Ukrainian: Верифікація

verifiability in Chinese:
形式化验证